“We are democratising custom silicon with reusable chiplets, enabling more companies to build their own silicon.”

In an exclusive interview,Mohit Gupta from TYLsemi explains to Saba Aafreen from Electronics For You as to why the future of AI infrastructure will depend on reusable chiplets, how they could make custom silicon practical beyond hyperscalers, and what this shift means for the next generation of semiconductor innovation.

Q. What inspired you to found TYLsemi, and what industry gap are you addressing?

A. After more than 22 years of building semiconductor chips, we realised there was a fundamental problem in how custom silicon was being developed. Artificial intelligence (AI) infrastructure is creating huge demand for specialised chips, but building custom silicon for central processing units (CPUs), graphics processing units (GPUs) and networking switches has become increasingly difficult due to physical limits, supply chain constraints and yield challenges at advanced process nodes. With the AI inference market expected to exceed a US$100 billion opportunity by 2030, we saw an opportunity to lower the cost and time required to develop custom silicon through reusable chiplets, making these capabilities accessible beyond hyperscalers. After helping build successful semiconductor businesses, including AlphaWave before its acquisition by Qualcomm in 2025, my co-founder Sunil and I felt this was the right time to build something of our own rather than miss the AI wave.

Q. Would you describe TYLsemi’s innovation as a technology innovation, a business innovation, or both?

A. I would say it’s both. From a business perspective, we are lowering the cost and time barriers to developing custom AI chips by providing foundational chiplet components, reducing the non-resident external (NRE) investment and making custom silicon accessible to companies whose core business isn’t semiconductors but still need application-specific chips. We also see this as an opportunity for India as interest in indigenous AI accelerators grows. From a technology perspective, we are building reusable chiplet blocks based on industry standards, allowing customers to focus on their architecture while we handle everything from chip design to qualified, tested silicon. We also optimise packaging and manufacturing choices to balance performance and cost, enabling organisations to build custom silicon without having to become semiconductor experts themselves.

Q. Why are chiplets becoming essential for next-generation AI infrastructure, and what makes TYLsemi different from others in the AI chiplet ecosystem?

A. Chiplets have become inevitable because advanced process nodes can no longer efficiently support large monolithic chips. As chips become larger, manufacturing costs increase, yields drop and scaling becomes much harder. At the same time, AI workloads require custom compute, while functions such as input/output (I/O), power and, eventually, memory can be reused as standard building blocks. That’s why companies building CPUs, GPUs, AI accelerators and network switches are all moving towards chiplet architectures. What sets TYLsemi apart is that we are democratising custom silicon with reusable chiplets, enabling more companies to build their own silicon.

Q. TYLsemi claims to reduce custom AI silicon development time and cost by up to 50 per cent. How do you achieve that?

A. This 50 per cent figure covers the full flow, from architecture through high-volume manufacturing, and it comes from starting with a production-ready portfolio instead of a blank sheet. We achieve this by disaggregating large AI chips into reusable chiplets. Functions such as I/O, power and memory can account for more than half of a chip’s area, but they don’t always need to be built on the latest process node and are already available as products from us. That means customers only need to develop their custom compute, while reusing these foundational blocks significantly reducing NRE costs, engineering effort and development time. It also addresses the industry’s shortage of experienced semiconductor talent, allowing engineering teams to focus on the part that truly differentiates their product instead of building every component from scratch.

Q. Could you walk us through TYLsemi’s TYL.IO, TYL.Power, TYL.Mem and TYL.Forge platform?

A. Our portfolio addresses the three core building blocks every AI chip needs. TYL.IO focuses on high-speed connectivity with PCIe Gen 7 chiplets, future scale-up interconnects for AI clusters and optical connectivity planned for next year. TYL.Power tackles one of the biggest challenges in AI data centres, energy efficiency, by optimising last-mile power delivery to the chip. Our goal is to save 300 to 500W on a 3kW accelerator, allowing operators to use that recovered power to deploy more compute. TYL.Mem, planned for next year, will address the growing memory bottleneck as AI compute continues to scale. Bringing all of these together is TYL.Forge, our integration platform that combines our chiplets with a customer’s compute architecture to deliver a qualified, cost-effective custom AI chip. Many of our customers are not semiconductor companies, so they can focus on their AI workloads while we handle the silicon implementation end to end.

Q. Which semiconductor technologies form the backbone of your platform?

A. Our initial silicon is being built on Taiwan Semiconductor Manufacturing Company’s (TSMC’s) leading process nodes, primarily 3nm, with 2nm and beyond planned for certain customer compute dies, while our power solutions are based on 16nm. On the packaging side, we are enabling technologies such as TSMC’s chip-on-wafer-on-substrate (CoWoS), integrated fan-out (InFO) and system on integrated chips (SoIC), while also exploring solutions from outsourced semiconductor assembly and test (OSAT) providers including ASE and Amkor, as well as Intel’s EMIB, to give customers multiple packaging options based on their performance and supply chain requirements.

Q. How do you validate interoperability and reliability across your chiplets?

A. Validation starts with standards. We build around open standards such as universal chiplet interconnect express (UCIe) and verify our designs using third-party verification IP and industry models to ensure they work as intended even before silicon is manufactured. The final step is integrating chiplets in a package and validating them together. While the industry is still evolving towards greater openness in sharing chiplets for cross-vendor testing, the combination of standardised interfaces and rigorous pre-silicon verification has already made reliable interoperability a practical reality, and we expect that collaboration to improve further over the next few years.

Q. What have been the biggest engineering challenges in building these chiplets, and how has your team addressed them?

A. The biggest engineering challenges are around power delivery, thermal management, reliability and advanced packaging, especially as AI accelerators continue to scale. These are industry-wide problems without complete solutions today, so we are working closely with our foundry, OSAT and ecosystem partners to develop them. Access to the right supply chain has also been critical, and our experience and industry relationships have helped us secure the same advanced technologies used by leading semiconductor companies. Beyond the technology, execution comes down to hiring experienced engineers who have built complex silicon before, so they can anticipate risks early, make the right trade-offs and put Plan A, Plan B and Plan C in place instead of reacting after issues arise.

Q. What are the biggest challenges in power delivery, thermal management and die-to-die communication for multi-chip AI systems?

A. As AI chips move into the kilowatt range, power delivery and thermal management have become some of the biggest engineering challenges. A chip can take years and hundreds of millions of dollars to develop, yet still fail if power isn’t delivered reliably to the transistors. Increasing compute, memory and connectivity also generates far more heat, making efficient cooling and power delivery inside the package critical. At TYLsemi, we are focused on optimising last-mile power delivery within the package while working closely with customers to solve real-world challenges. We deliberately chose power, I/O and memory because these are long-standing industry bottlenecks that will remain critical as AI systems continue to scale.

Q. How important is UCIe to your long-term architecture?

A. UCIe is fundamental to our architecture because we believe in open standards that enable broader adoption rather than proprietary ecosystems. Before UCIe, the chiplet ecosystem was fragmented, with different die-to-die interconnect standards limiting interoperability. The industry came together to create UCIe, much like PCIe and Ethernet became universal standards, making chiplet integration far more practical. We are building our chiplets around UCIe while also supporting standards such as PCIe, Ethernet, LPDDR and HBM. The widespread adoption of UCIe by hyperscalers has been one of the key enablers for TYLsemi, allowing us to build interoperable chiplets that can seamlessly integrate into customers’ designs.

Q. Why did you choose the name TYLsemi, and what does it represent?

A. The name reflects our core focus on chiplet “tiles”, which are becoming the fundamental building blocks of modern semiconductor design. Early in my career, the industry’s goal was to integrate more functionality into a single monolithic chip, but at advanced nodes like 3nm and 2nm, we’ve reached practical limits, especially for high-performance computing and networking. That has shifted the industry towards chiplet-based architectures, something I’ve believed in since around 2016–17, well before it became mainstream. Today, major AI chips from companies like NVIDIA, Google, Meta, and Microsoft all leverage chiplets, so we wanted that philosophy to sit at the centre of our strategy. We chose “Tile” as the foundation of our name and stylised it as “TYL” with the aspiration that it could one day become a recognisable stock symbol, while reinforcing our belief that chiplets represent the future of semiconductor design.

Q. Could you briefly introduce the founding team and your backgrounds?

A. TYLsemi was founded by myself and Sunil Bhadwaj. Most recently, I was at Qualcomm following the acquisition of AlphaWave, where I led the custom silicon and IP business after helping grow AlphaWave nearly fivefold in three years. Earlier, I worked at SiFive and Rambus, where Sunil and I first met around 12 years ago. While I focus on business, strategy and products, Sunil leads engineering and silicon operations, making our skills highly complementary. Together, we have delivered over 75 chip designs and shipped more than 30 million chips through foundries such as TSMC. Our leadership team also includes Shashank Desai, formerly with Microsoft’s cloud AI accelerator team, and Sandeep Gupta, who leads our India operations. One thing we strongly believe in is that India is not just a design centre. We have successfully taped out chips from Bengaluru before, and we want India to remain a core part of innovation and product development at TYLsemi.

Q. Could you share a few quick facts about TYLsemi, including its headquarters, legal structure and current team size?

A. TYLsemi is a US-headquartered company based in San Jose, with a newly opened office in Bengaluru and plans to expand into Taiwan in the second half of this year. The US entity is the parent company, with a subsidiary in India and another planned for Taiwan. Although the company is only four months old, we’ve grown rapidly from a one-person startup to around 35 employees, with another 20 joining soon and 10 to 15 contractors supporting us. Our goal is to reach about 100 people by the end of the year, with around 60 per cent of the team based in India, and grow to more than 200 employees globally by the end of next year. Taiwan will play an important role in our operations as we build on our longstanding relationship with TSMC and its advanced technologies.

Q. Was the platform developed entirely in-house, or did you collaborate with IP vendors and ecosystem partners?

A. It has always been an ecosystem effort because building advanced semiconductor platforms cannot be done in isolation. While our core differentiation and chiplet technologies are being developed in-house, we are working with IP vendors, electronic design automation (EDA) companies, foundry and packaging partners, and will be announcing some of these collaborations in the coming months. In areas such as power delivery, for example, we rely on ecosystem partners for sensing and monitoring technologies, while manufacturing is supported by TSMC and OSAT partners. Our approach is to build what differentiates us and collaborate where it accelerates innovation and execution.

Q. Has academia or research collaboration contributed to your technology development?

A. It’s still early days, so we haven’t formally collaborated with academia yet, but it’s a key part of our long-term strategy. We see strong opportunities to work with universities, particularly in research areas such as optics and power, where the challenges are complex and require long-term innovation. We are looking at partnerships in both India and the US, and while nothing has been announced yet, we expect to begin formal academic collaborations in the first quarter of next year.

Q. Why did you establish an engineering centre in Bengaluru, and what role will India play in your global roadmap?

A. India has always been central to our strategy because of its exceptional semiconductor talent, strong engineering culture and growing ambition to build complex technologies. We chose Bengaluru for its deep talent pool, but our vision extends beyond one city, with plans to expand across India as we grow and even explore opportunities in Tier 2 cities. Beyond execution, we also see India as an emerging market for AI infrastructure, backed by strong government support for semiconductors. Our philosophy is that India is not just a design centre, but an equal part of our global engineering organisation. We’ve taped out advanced chips from India before and will continue to do so, while fostering a people-first culture that gives engineers ownership, visibility and the opportunity to work on cutting-edge semiconductor products.

Q. What policy support or ecosystem improvements are still needed to accelerate chiplet innovation?

A. Greater interoperability and openness across the industry would significantly accelerate chiplet adoption. While standards such as UCIe have made strong progress, broader collaboration and a willingness to share across the ecosystem will make integration much easier. From a policy perspective, a more geographically diverse semiconductor supply chain would also be a major advantage. As countries such as India strengthen their manufacturing capabilities, companies will have greater flexibility in sourcing different parts of the silicon stack, reducing supply risks and encouraging more innovation by lowering the barriers and uncertainty around chip development.

Q. Could you tell us about your fundraising journey and what convinced investors to back TYLsemi?

A. This was my first time leading a fundraising round, and the response was overwhelming. What stood out to investors wasn’t just the market opportunity, which everyone already recognised, but the conviction of the founding team, the real industry problem we were solving and our track record in semiconductors. We were equally selective about our investors, looking for partners who could contribute strategic value alongside capital. That’s why we brought together a mix of financial and ecosystem investors, including Matter Venture Partners, Viola Ventures, GHOVC and Taiwan-based EG Tech, along with another undisclosed strategic investor. The round was oversubscribed, allowing us to raise nearly $43 million, more than initially planned, to support the capital-intensive nature of the business, with a Series A expected next year.

Q. Are you currently looking for technology or ecosystem partners, and what would an ideal partner look like?

A. We strongly believe in building through partnerships because no one succeeds alone in the semiconductor ecosystem. We are looking to collaborate with companies developing AI infrastructure, especially those that want to build custom silicon but need the right semiconductor partner. We are also interested in working with OSAT providers to expand chiplet packaging options, as well as companies building AI-powered chip design tools that can improve engineering productivity. Any partner that helps accelerate custom silicon development, whether through technology, manufacturing or design automation, is someone we’d be excited to work with.

Q. What is the biggest technical or business challenge you must overcome to scale rapidly?

A. The biggest challenge is execution. We need to engage with more customers, deliver on our commitments and manage the risks that come with building a complex semiconductor business. The market opportunity is strong, so our focus is on staying disciplined, executing well and building the right technology. Challenges will always exist, but as engineers, we believe every challenge has a solution.

Q. What advice would you give young engineers and entrepreneurs looking to build deep-tech semiconductor startups?

A. Semiconductors are fundamentally an ecosystem business, so don’t expect to succeed alone. Build strong relationships across the global semiconductor value chain and surround yourself with the right partners. For engineers, I’d encourage more people to pursue semiconductor design while continuously embracing AI-driven design tools, because the industry is changing rapidly and those who use AI effectively will stay ahead. For entrepreneurs, focus on solving long-term problems rather than chasing short-term trends. Look at challenges that will still matter a decade from now, because those are the foundations on which enduring deep-tech companies are built.

My message, especially to people in semiconductors, is to be bold and ambitious. Building semiconductor companies requires significant investment and comes with tough engineering challenges, but if it were easy, everyone would do it. AI will solve some problems, but it will also create many new ones. Our belief at TYLsemi is to stay ahead of that curve by tackling the hard problems that matter for the future, not the ones that have already been solved.