Taiwan's AblePrint targets advanced packaging shift with warpage control technology

TAIPEI (Taiwan News) — Taiwanese semiconductor equipment manufacturer AblePrint Technology is targeting growth opportunities as the chip industry shifts from wafer-level processes toward larger panel-level packaging.

The transition is being driven by AI chip development, which requires higher computing performance and greater bandwidth. However, producing larger substrates introduces new manufacturing challenges, such as maintaining substrate flatness during processing, according to CTEE and Sinotrade.

While AblePrint is widely known for equipment that removes trapped air bubbles during chip assembly, the company has expanded into warpage control, addressing the bending of substrates that can occur during high-temperature manufacturing steps.

Its system is designed to support several emerging packaging technologies as they move toward mass production, including chip-on-panel packaging (CoPoS), fan-out panel-level packaging (FOPLP), glass substrates, and hybrid bonding.

During semiconductor packaging, high-temperature processes can cause different materials to expand and contract at different rates. This mismatch creates stress that may lead to substrate warpage, which can affect later processes such as bonding and cutting. Controlling warpage is essential for maintaining production yields and manufacturing accuracy.

AblePrint expects the importance of related equipment to increase alongside the growing complexity of advanced packaging. The company said its high-pressure vacuum debubbling equipment remains a key contributor to revenue, while platform-based process equipment and warpage suppression systems are expected to see wider adoption.

AblePrint reported June revenue of NT$230 million (NT$7.15 million), down 6.43% from the same period last year. First-half revenue reached a record NT$1.79 billion, an increase of 63.09% from a year earlier.

CoPoS has attracted industry attention for its use of larger square panels instead of traditional round wafers. By increasing the processing area, panel-level packaging could allow more chips to be packaged simultaneously, improving production efficiency.

Glass substrates have also emerged as a potential solution for next-generation high-performance packaging because they can support higher-density interconnects and improved electrical performance. However, producing larger glass substrates presents challenges in maintaining structural stability throughout the manufacturing process.