JEDEC LPDDR6 Revision: AI Data Center Features, SOCAMM2, and PIM Technology

JEDEC LPDDR6 Revision Targets AI Data Center Growth with New Features

An upcoming revision of the LPDDR6 standard from JEDEC will incorporate several capabilities tailored to the memory's rising adoption in AI data centers. Historically linked to smartphones, tablets, and slim laptops, LPDDR supply is now increasingly directed toward power-conscious AI data centers. Since the release of the foundational JESD209-6 specification in July 2025, the JC-42.6 Subcommittee has worked to broaden LPDDR6 beyond mobile uses to support data center and accelerated computing tasks that demand power-efficient, high-capacity memory.

Hung Vuong, chair of the JC-42.6 Subcommittee for Low Power Memories, stated that boosting performance while cutting power consumption is central to any JEDEC memory standard. He noted that data center clients show strong interest in LPDDR, and this revision will emphasize features addressing their requirements. Osamu Nagashima, the subcommittee's vice-chair, highlighted a narrower x6 per-die interface as a key addition, enabling greater capacities. He described the bandwidth gain as modest—roughly 10 to 20 percent over the prior version—but stressed that densities can be doubled. Adopting a non-binary interface width and an extra x6 sub-channel mode permits more die per package and higher memory capacities per component and per channel. Nagashima indicated a target of 512GB density, exceeding the current LPDDR5/5X maximum, to meet the growing memory needs of AI training and inference workloads.

The update will also introduce an LPDDR6 SOCAMM2 module standard, aimed at improving the compact, serviceable module form factor and offering a clear upgrade path from existing LPDDR5X SOCAMM2 modules. SOCAMM addresses AI systems' energy and space limitations by delivering 2.5 times the bandwidth of conventional modules while using about one-third less energy. Earlier in 2026, Micron Technology launched a 256GB SOCAMM2, a data center-class modular LPDDR5X memory module for AI infrastructure. JEDEC is also finalizing a standard for LPDDR6 processing-in-memory (LPDDR6 PIM) technology, which aligns with the broader LPDDR6 roadmap. Vuong explained that LPDDR6-PIM integrates compute logic directly into the memory chip, enabling the memory to perform calculations rather than just store data, thereby offloading some processing tasks. Nagashima added that this reduces data movement between CPU/GPU and RAM, a key bottleneck for AI workloads, while also lowering power consumption.

Vuong observed that LPDDR has been evolving into a data center memory over the past five years, shifting from a primarily mobile, solder-on solution for smartphones to client computing as firms like Dell, Lenovo, and HP recognized the benefits of LPDDR5 technology. He noted that LPDDR6 and SOCAMM have drawn interest from data center customers as power consumption becomes a more critical factor, adding that AI and data centers are currently driving or straining the ecosystem. Vuong reported substantial pressure from these users to update the LPDDR6 standard, along with strong collaboration to move it forward. He stated that most features are already set, and the subcommittee is now finalizing the details.